Showing posts with label Vendor SuperMicro. Show all posts
Showing posts with label Vendor SuperMicro. Show all posts

Friday, 19 February 2021

Open RAN (O-RAN) RRU (O-RU) and DU (O-DU) Design


We often publish Open RAN related information on this blog. Now, Telefónica has just published a whitepaper providing an overview of the main technology elements that it is developing in collaboration with selected partners in the Open RAN ecosystem. 

It describes the architectural elements, design criteria, technology choices and key chipsets employed to build a complete portfolio of radio units and baseband equipment capable of a full 4G/5G RAN rollout in any market of interest. More details here and the PDF is here.

The following is a selective abstract from the paper:

Sites within Telefónica footprint can be broadly classified into four types, from low/medium capacity 4G to high/dense capacity 4G+5G, as illustrated in Figure 1. Each of those types correspond to a particular arrangement of DUs and RRUs whose design and dimensioning represents a key milestone that must be achieved prior to any further development. Representative frequency bands are just shown for illustration purposes, as well the number of cells that can be typically found in each site type.

3GPP defined a new architectural model in Release 15, where the gNB is logically split into three entities denoted as CU, DU and RRU. The RAN functions that correspond to each of the three entities are determined by the so-called split points. After a thorough analysis of the potential split options, 3GPP decided to focus on just two split points: so-called split 2 and split 7, although, only the former one was finally standardized. The resulting partitioning of network functions is shown in Figure 2.

The CU (Centralized Unit) hosts the RAN functions above split 2; the DU (Distributed Unit) runs those below split 2 and above split 7; and the RRU hosts the functions below split 7 as well as all the RF processing.

The O-RAN Alliance further specified a multi-vendor fronthaul interface between the RRU and DU, by introducing a specific category of split 7 called split 7-2x, whose control, data, management, and synchronization planes are perfectly defined. The midhaul interface between CU and DU is also specified by 3GPP and further upgraded by the O-RAN Alliance to work in multivendor scenarios.

The CU and DU can be co-located with the RRU (Remote Radio Unit) in purely distributed scenarios. However, the real benefit of the split architecture comes from the possibility to centralize the CU, and sometimes also the DU, in suitable data centers where all RAN functions can be fully virtualized and therefore run on suitable servers.

The infrastructure needed to build a DU is nothing else than a server based on Intel Architecture optimized to run those real-time RAN functions located below split 2, and to connect with the RRUs through a fronthaul interface based on O-RAN split 7-2x. It is the real-time nature of the DU which motivates the need to optimize the servers required to run DU workloads.

The DU hardware includes the chassis platform, mother board, peripheral devices, power supply and cooling devices.

When the DU must be physically located inside a cabinet, the chassis platform must meet significant mechanical restrictions like a given DU depth, maximum operating temperature, or full front access, among others. The mother board contains processing unit, memory, the internal I/O interfaces, and external connection ports. The DU design must also contain suitable expansion ports for hardware acceleration. Other hardware functional components include the hardware and system debugging interfaces, and the board management controller, just to name a few. Figure 3 shows a functional diagram of the DU as designed by Supermicro.

In the example shown above, the Central Processing Unit (CPU) is an Intel Xeon SP system that performs the main baseband processing tasks. To make the processing more efficient, an ASIC based acceleration card, like Intel’s ACC100, can be used to assist with the baseband workload processing. The Intel-based network cards (NICs) with Time Sync capabilities can be used for both fronthaul and midhaul interfaces, with suitable clock circuits that provide the unit with the clock signals required by digital processing tasks. PCI-e slots are standard expansion slots for additional peripheral and auxiliary cards. Other essential components not shown in the figure are randomaccess memory (RAM) for temporary storage of data, flash memory for codes and logs, and hard disk devices for persistent storage of data even when the unit is powered-off.

An Open RAN Remote Radio Unit (RRU) is used to convert radio signals sent to and from the antenna into a digital baseband signal, which can be connected to the DU over the O-RAN split 7-2x fronthaul interface.

For illustration, the reference architecture of an Open RAN RRU from Gigatera Communications is shown in Figure 7. It shows the functional high-level diagram of the RRU containing the following components:

  • Synchronization and Fronthaul Transport Functional Block
  • Lower PHY Layer Baseband Processing Functional Block
  • Digital Front End (DFE) Functional Block
  • RF Front End (RFFE) Functional Block

For more details, check out the whitepaper here.

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Monday, 20 April 2020

SuperMicro's 5G Pole-Mounted DU Server Solution

Back in December 2019, Supermicro launched Server Class Edge Systems for Open 5G Radio Access Network (RAN) Solutions. These new SuperServers offer O-RAN Open-Platform Software, Intel Xeon Scalable Processors, GPUs, FPGA and IP65-rated protective enclosures for Pole-Mounted Cell Tower Deployments. The solutions for 5G cell tower deployments leverage fully-configurable SuperServers based on 2nd Gen Intel Xeon Scalable processors and Intel Xeon D processors, O-RAN compliant partner software, and ability to operate in harsh environments. These capabilities accelerate the mobile network evolution from proprietary hardware/software to open source software and disaggregated hardware for 5G installations.


The press release states:

“Supermicro’s data center customers and global telecommunication operators are asking for non-proprietary disaggregated hardware and software 5G solutions supporting multi-vendor web-scale networks, said Charles Liang, president, and CEO of Supermicro. “Supermicro’s new SuperServer solutions provide the 5G network infrastructure with maximum deployment flexibility and efficient total cost of ownership (TCO).”

Supermicro’s two new systems are its first servers for 5G, the Intelligent Edge, and other embedded applications to be based on 2nd Gen Intel Xeon processors. The E403-9P-FN2T is built for demanding environments and includes three PCI-E slots for GPU and FPGA accelerator cards. The compact 1U 1019P-FHN2T is well-suited for controlled environments such as micro data centers and re-purposed central office locations and features two full-height full-length PCI-E slots.

With these expansion slots, Supermicro can provide real-time Edge AI inferencing via GPU cards, and accelerate 5G RAN software and open-standard site-to-site communication using the Intel FPGA Programmable Acceleration Card N3000. These new servers complement Supermicro’s successful Intel Xeon D-based 1019D and E403 models. Supermicro is developing IP65-rated protective enclosures to meet the needs of outdoor environments such as cell towers and microcell sites.


5G Physical Layer splits can be seen in the picture above. While 4G used the BBU + RRU/RRH architecture, 5G will have a Central Unit (CU) and a Distributed Unit (DU). A Radio Unit (RU) may be present in some scenarios as well.

The Outdoor Edge Systems page on their website provides more information about the Pole-Mounted IP65 Server Platform for 5G and the Intelligent Edge. We will end with a video that depicts their vision



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